Design of Robust and Power Efficient Full Adder Using Energy Efficient Feed through Logic

An Energy Efficient Feedthrough Logic (EE-FTL) is proposed in this paper to reduce the power consumption for low power applications. The EE-FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style requires low power when compare to the existing feedthrough logic (FTL). The proposed circuit is simulated and a comparison analysis has been carried out using 90-nm, 1.2V CMOS process technology. A CMOS Full Adder is designed by the energy efficient feedthrough logic and the simulation result in MicroWind environment shows that the proposed logic reduces the power consumption by 77%, 70% and 36% over FTL, Low Power FTL (LP-FTL) and Constant Delay Logic (CDL), respectively. The problem of requirement of inverter as in dynamic logic is completely eliminated in the proposed logic. Keywords— Feedthrough logic(FTL), critical path, pre-evaluated, constant delay. INTRODUCTION Energy efficiency is one of the most required features for modern electronic systems designed for high-performance and portable applications. In one hand, the ever increasing market segment of portable electronic devices demands the availability of low-power building blocks that enable the implementation of long-lasting battery-operated systems. The invention of the dynamic logic in the 80s is one of the answers to this request as it allows designers to implement high performance circuit block, i.e., arithmetic logic unit (ALU), at an operating frequency that traditional static and pass transistor CMOS logic styles are difficult to achieve. However, the performance enhancement comes with several costs, including reduced noise margin, charge-sharing noise, and higher power dissipation due to higher data activity. Because of dynamic logic's limitations and diminished speed reward, a slowly rising need has emerged in the past decade to explore new logic style that goes beyond dynamic logic. To improve the performance of dynamic logic circuit in terms of speed and power, new logic family called feedthrough logic was proposed in [4], where FTL concept is extended for the design of low power and high performance arithmetic circuits. This logic works on domino concept along with the important feature that output is partially evaluated before all the inputs are valid. This feature results in very fast evaluation in computational block. In this paper, the proposed design of a low power FTL circuit that further improves the power consumption of FTL. The total power dissipated in a generic CMOS digital gate is given by Ptotal =Pstatic+Pdynamic+Pshort circuit =VddIi+VddFclk ΣVi swing Ci load αi+Vdd Σ Ii sc Where V i swing is the voltage swing, C i load is the load capacitance, αi the switching factor, I i sc is the short circuit current and I I is the leakage current at node i respectively and Fclk denotes the system clock frequency. II. PRINCIPLE OF CONVENTIONAL FTL FTL logic [Fig.1 (b)] in CMOS technology was first introduced in [4] and [5]. Its basic operation is as follows: when CLK is high, the pre-discharge period begins and Out is pulled down to GND through M2. When CLK becomes low, M1 is on, M2 is off, and the gate enters the evaluation period. If inputs (IN) are logic ―1,‖ Out enters the contention mode where M1 and transistors in the NMOS PDN are conducting current simultaneously. If PDN is off, then the output quickly rises to logic ―1.‖  It only requires NMOS transistor logic expression  The critical path is constant regardless of the logic expression International Journal of Engineering Research and General Science Volume 2, Issue 2, Feb-Mar 2014 ISSN 2091-2730 97 www.ijergs.org  The output is pre-evaluated before the inputs from the preceding stage is ready Fig.1 (a) Dynamic Domino Logic (b) FTL Despite its performance advantage, FTL suffers from reduced noise margin, excess direct path current, and nonzero nominal low output voltage, which are all caused by the contention between M1 and NMOS PDN during the evaluation period. Furthermore, cascading multiple FTL stages together to perform complicated logic evaluations is not practical. Consider a chain of inverters implemented in FTL cascaded together and driven by the same clock. When CLK is low, M1 of every stage turns on, and the output of every stage begins to rise. This will result in false logic evaluations at even numbered stages since initially there is no contention between M1 and NMOS PDN because all inputs to NMOS transistors are reset to logic ―0‖ during the reset period. Existing FTL Techniques 1. LP-FTL The low power FTL circuit is shown in Figure 2 (a). This circuit reduces VOL by using one additional PMOS transistor MP2 in series with MP1. The operation of this circuit is similar to that of FTL. During reset phase i.e. when CLK = 1, output node is pulled to ground (GND) through Mr. During evaluation phase output node charges through Mp1 and Mp2. When CLK goes low (evaluation phase) Mr is turned off and the output node conditionally evaluates to logic high (VOH) or low (VOL) depending upon input to NMOS block. If the NMOS block evaluates to high then output node pulled toward VDD i.e. VOH =VDD, otherwise it remain at logic low i.e. VOL. Since Mp1 and Mp2 are in series the voltage at drain of MP1 is less than VDD. During evaluation due to ratio logic the output node pulled to logic low voltage i.e. VOL which is less than the VOL of existing FTL. This reduction in VOL causes significant reduction in dynamic power consumption but due to the insertion of PMOS transistor Mp2 propagation delay of the LP-FTL increases.